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triple - channel, digital isolators, enhanced system - level esd reliability data sheet adum3300/adum3301 features enhanced system - level esd performance per iec 61000 -4-x low power operation 5 v operation 2.0 ma per channel maximum at 0 mbps to 2 mbps 4.1 ma per channel maximum at 10 mbps 36 ma per channel maximum at 90 mbps 3 v operation 1.0 ma per channel ma ximum at 0 mbps to 2 mbps 2.8 ma per channel maximum at 10 mbps 17 ma per channel maximum at 90 mbps bidirectional communication 3 v/5 v level translation high temperature operation: 105c high data rate: dc to 90 mbps (nrz) precise timing characteristics 2 ns maximum pulse width distortion 2 ns maximum channel - to - channel matching high common - mode transient immunity: >25 kv/s output enable function 16- lead soic wide body, rohs - compliant package safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884 - 10 (vde v 0884 - 10): 2 006 - 12 v iorm = 560 v peak applications general - purpose multichannel isolation spi interface/data converter isolation rs- 232/rs - 422/rs - 485 transceivers industrial field bus isolation general description the adum330x 1 are 3 - channel digital iso lators based on the an a log devices, inc. , i coupler? technology. combining high speed cmos and monolithic air core transformer technology, these isolation components provide outstanding performance chara c teristics superior to alternatives, such as optocoupl er devices. i coupler devices remove the design difficulties commonly associated with optocouplers. typical optocoupler concerns regarding u n certain current transfer ratios, nonlinear transfer functions, and te m perature and lifetime effects are eliminated w ith the simple i coupler digital interfaces and stable performance characteri s tics. the need for external drivers and other discrete components is eliminated with these i coupler products. furthermore, i coupler devices consume one - tenth to one - sixth the powe r of optoco u plers at comparable signal data rates. the adum330x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the ordering guide ). all models operate with the su p ply voltage on either side ranging from 2.7 v to 5.5 v, pr o viding compatibility with lower voltage systems as well as en a bling a voltage translation functionality across the isolation ba rrier. the adum330x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power - up/power - down conditions. in compariso n to adum130x isolators, adum330x isolators contain various circuit and layout changes to provide increased capability relative to system - level iec 61000 -4- x testing (esd, burst, and surge). the precise capability in these tests for either the adum130x or adum330x products is strongly determined by the design and layout of the users system. 1 protected by u.s. patents 5 , 952, 849 ; 6, 873, 065 ; 6,903,578 ; and 7 ,075,329 . functional block dia grams encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic nc nc gnd 1 v dd2 gnd 2 v oa v ob v oc nc v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05984-001 f igure 1 . adum3300 func tional block diagram decode encode encode decode encode decode v dd1 gnd 1 v ia v ib v oc nc v e1 gnd 1 v dd2 gnd 2 v oa v ob v ic nc v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05984-002 f igure 2 . adum3301 functional block diagram r ev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2006C 2014 analog devices, inc. all rights reserved. technical support www.analog.com
adum3300/adum3301 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v operation ................................ 3 electrical characteristics 3 v operation ................................ 5 electrical characteristics mixed 5 v/3 v or 3 v/5 v operation ....................................................................................... 7 package characteristics ............................................................. 10 regulatory information ............................................................. 10 insulation and safet y - related specifications .......................... 10 din v vde v 0884 - 10 (vde v 0884 - 10) insulation characteristics ............................................................................ 11 recommended operating conditions .................................... 11 absolute maximum ratings ......................................................... 12 esd caution ................................................................................ 12 pin configurations and function descriptions ......................... 13 typical performance characteristics ........................................... 15 application information ................................................................ 17 pc board layout ........................................................................ 17 system - level esd considerations and enhancements ........ 17 propagation delay - related parameters ................................... 17 dc correctness and magnetic field immunity ........................... 17 power consumption .................................................................. 18 insulation lifetime ..................................................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision hist ory 4/14 rev. b to rev. c change to table 5 ........................................................................... 10 2/ 12 rev. a to rev. b created hyperlink for safety and regulatory approvals entry in features section ................................................................. 1 change to pc board layout se ction ............................................ 17 updated outline dimensions ....................................................... 20 6/07 rev. 0 to rev. a updated vde certification throughout ...................................... 1 changes to features, general description, and note 1 ............... 1 changes to regulatory information section .............................. 10 changes to din v vde v 0884 - 10 (vde v 0884 - 10) insulation characteristics .............................................................. 11 added table 10 ............................................................................... 12 added insulation lifetime section .............................................. 19 3/06 revision 0: initial version rev. c | page 2 of 20
data sheet adum3300/adum3301 specifications electrical character istics 5 v operation all voltages are relative to their respective ground. 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over t he entire recommended operation range, unless othe r wise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. table 1. parameter symbol min typ max unit test conditions dc specifications input supply curren t per channel, quiescent i ddi (q) 0.66 0.97 ma output supply current per channel, quiescent i ddo (q) 0.39 0.55 ma adum3300 , total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 2.4 3.3 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.1 2.1 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 7.0 8.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 2.7 3.6 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 54 77 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 15 31 ma 45 mhz logic signal freq. adum3301 , total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 2.0 3.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i d d2 (q) 1.6 2.3 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5.5 6.9 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 3.9 5.4 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 41 57 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 28 41 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 2.0 v logic low input threshold v il , v el 0.8 v logic high output voltages v oah , v obh , v och , v odh (v dd1 or v dd2 ) ? 0.1 5.0 v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0 .4 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum330x arw z minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 65 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel -to - channel matching 6 t pskcd/od 50 ns c l = 15 pf, cmos signal levels rev. c | page 3 of 20
adum3300/adum3301 data sheet parameter symbol min typ max unit test conditions adum330x brw z minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal lev els propagation delay 4 t phl , t plh 20 32 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 15 ns c l = 15 pf, cmos signal levels channel -to - channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel -to - channel matching, opposing - directional channels 6 t pskod 6 ns c l = 15 pf, cmos s ignal levels adum330x crwz minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 18 27 32 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos sig nal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 10 ns c l = 15 pf, cmos signal levels channel -to - channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel -to - channel matching, opposing - directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/lo w- to - high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance -to - high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signa l levels common - mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common - mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current per channel 8 i ddi (d) 0.20 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.05 ma/mbps 1 the supply current values for all four channels are combined when running at identical data rates. output supply current values are specified with no output load present. the supply current associated with an individual channel operating at a given data rate can be calculated as describ ed in the power consumption section. see figure 6 through figure 8 for information on per - channel supply current as a function of data rate for unloaded and loaded conditions. see figure 9 through figure 12 for total v dd1 and v dd2 supply currents as a function of data rate for adum3300 / adum3301 channel co nfigurations. 2 the minimum pulse widt h is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagatio n delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional chan nel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrier. opposing - directional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common - mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. the tra n sient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the i ncremental amount of supply current required for a 1 mbps increase in signal data rate. see figure 6 through figure 8 for information on per - channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per - channel su p ply current for a given data rate. rev. c | page 4 of 20
data sheet adum3300/adum3301 elect rical characteristic s 3 v operation all voltages are relative to their respective ground. 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v; all minimum/maximum specifications apply over the entire recommended operation range, unless othe r wise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v. table 2. par ameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.37 0.57 ma output supply current per channel, quiescent i ddo (q) 0.25 0.37 ma adum3300 , total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.4 1.9 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.7 1.2 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 3.8 5.3 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.5 2.1 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 28 41 ma 45 mhz logic sign al freq. v dd2 supply current i dd2 (90) 8.2 11 ma 45 mhz logic signal freq. adum3301 , total supply current, four channels 1 dc to 2 mbps v d d1 supply current i dd1 (q) 1.1 1.6 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.9 1.4 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 3.0 4.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 2.2 2.9 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 22 31 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 15 21 ma 45 mhz logic signal freq. for all models inp ut currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 ,v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 1.6 v logic low input threshold v il , v el 0.4 v logic high output voltages v oah , v obh , v och , v odh (v dd1 or v dd2 ) ? 0.1 3.0 v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 2.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum330x arw z minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 75 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel -to - channel matching 6 t pskcd/od 50 ns c l = 15 pf, cmos signal levels rev. c | page 5 of 20
adum3300/adum3301 data sheet par ameter symbol min typ max unit test conditions adum330x brw z minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal lev els propagation delay 4 t phl , t plh 20 38 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 22 ns c l = 15 pf, cmos signal levels c hannel-to - channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel -to - channel matching, opposing - directional channels 6 t pskod 6 ns c l = 15 pf, cmos s ignal levels adum330x crwz minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 34 45 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos sig nal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 16 ns c l = 15 pf, cmos signal levels channel -to - channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel -to - channel matching, opposing - directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/l ow-to - high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance -to - high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 3 ns c l = 15 pf, cmos signal levels common - mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common - mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current per channel 8 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.03 ma/mbps 1 the supply current values for all four channels are combined when running at identical data rates. output supply curren t values are specified with no output load pr e sent. the supply current associated with an individual channel operating at a given data rate can be calculated as described in the power consumption section. see figure 6 through figure 8 for information on per - channel supply current as a function of data rate for unloaded and loaded conditions. see figure 9 through figure 12 fo r t otal v dd1 and v dd2 supply currents as a function of data rate for adum3300 / adum3301 channel configurations. 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. opposing - directional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common - mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. the tra n sient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amount o f supply current required for a 1 mbps increase in signal data rate. see figure 6 through figure 8 for information on per - channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per - channel su p ply current for a given data rate. rev. c | page 6 of 20
data sheet adum3300/adum3301 electri cal characteristics mixed 5 v/3 v or 3 v /5 v operation all voltages are relative to their respective ground. 5 v/3 v operation: 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v. 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v. a ll minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. a ll typical specifi cations are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v or v dd1 = 5 v, v dd2 = 3.0 v. table 3. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quie s cent i ddi (q) 5 v/3 v operation 0.66 0.97 ma 3 v/5 v operation 0.37 0.57 ma output supply current per channel, quiescent i ddo (q) 5 v/3 v operation 0.25 0.37 ma 3 v/5 v operation 0.39 0.55 ma adum3300 , total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.4 3.3 ma dc to 1 mhz logic si g nal freq. 3 v/5 v operation 1.4 1.9 ma dc to 1 mhz logic si g nal freq. v dd2 supply cu rrent i dd2 (q) 5 v/3 v operation 0.7 1.2 ma dc to 1 mhz logic si g nal freq. 3 v/5 v operation 1.1 2.1 ma dc to 1 mhz logic si g nal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 7.0 8.1 ma 5 mhz logic signal freq. 3 v/5 v operation 3.8 5.3 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 1.5 2.1 ma 5 mhz logic signal freq. 3 v/5 v operation 2.7 3.6 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 54 77 ma 45 mhz logic signal freq. 3 v/5 v operation 28 41 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 8.2 11 ma 45 mhz logic signal freq. 3 v/5 v operation 15 31 ma 45 mhz logic signal freq. adum3301 , total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.0 3.1 ma dc to 1 mhz logic si g nal freq. 3 v/5 v operation 1.1 1.6 ma dc to 1 mhz logic si g nal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 0.9 1.4 ma dc to 1 mhz logic si g nal freq. 3 v/5 v operation 1.6 2.3 ma dc to 1 mhz logic si g nal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 5.5 6.9 ma 5 mhz logic signal freq. 3 v/5 v operation 3.0 4.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 2.2 2.9 ma 5 mhz logic signal freq. 3 v/5 v operation 3.9 5.4 ma 5 mhz logic signal freq. rev. c | page 7 of 20
adum3300/adum3301 data sheet parameter symbol min typ max unit test conditions 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 41 57 ma 45 mhz logic signal freq. 3 v/ 5 v operation 22 31 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 15 21 ma 45 mhz logic signal freq. 3 v/5 v operation 28 41 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 5 v/3 v operation 2.0 v 3 v/5 v operation 1.6 v logic low input threshold v il , v el 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v logic high output voltages v oah , v obh , v och , v odh (v dd1 or v dd2 ) ? 0.1 (v dd1 or v dd2 ) v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 (v dd1 or v dd2 ) ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum330x arw z minim um pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 70 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel -to - channel matching 6 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum330x brw z minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 15 35 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 22 ns c l = 15 pf, cmos signal levels channel -to - channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel -to - channel matching, oppo s ing - directional channels 6 t pskod 6 ns c l = 15 pf, cmos sign al levels adum330x crwz minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 30 40 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 14 ns c l = 15 pf, cmos signal levels channel -to - channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel -to - channel matching, oppo s ing - directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels rev. c | page 8 of 20
data sheet adum3300/adum3301 parameter symbol min typ max unit test conditions for all models output disable propagation delay (h igh/low -to - high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance -to - high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f c l = 15 pf, cmos sign al levels 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns common - mode transient immunity at logic high output 7 |cm h | 25 35 k v/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common - mode transient immunity at logic low outp ut 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, tra n sient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 m bps 3 v/5 v operation 1.1 m bps input dynamic supply current per channel 8 i ddi (d) 5 v /3 v operation 0.20 m a/mbps 3 v/5 v operation 0.10 m a/mbps output dynamic supply current per channel 8 i ddo (d) 5 v/3 v operation 0.05 ma/mbps 3 v/5 v operation 0.03 ma/mbps 1 the supply current values for all four channels are combined when running at identical data rates. output supply current valu es are specif ied with no output load present. th e s upply cu r rent a s socia ted with an in di vi dual ch annel o perating a t a given d ata ra te can be ca lculated a s described i n t he power c onsumption section. see figure 6 through figure 8 f or information on per-c ha nnel supply current as a function of data rate for unloaded and loaded conditions. see figure 9 through figure 12 for total v dd 1 a nd v dd 2 supp l y currents as a function of data rate for adum3300/adum3301 channel configurations. 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data ra te at which the specified pulse width di stortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrier. opposing - directional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common - mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amount of supply current required for a 1 mbps increase in signal data rate. see figure 6 through figure 8 for information on per - channel supply curre nt for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per - channel supply current for a given data rate. rev. c | page 9 of 20
adum3300/adum3301 data sheet package characterist ic s table 4. parameter symbol min typ max unit test conditions resistance (input to output) 1 r i-o 10 12 ? capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction -to - case thermal resistance, side 1 jci 33 c/w thermocouple located at center of package underside ic junction -to - case thermal resistance, side 2 jco 28 c/w 1 the device is considered a 2 - terminal device; pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory informati on the adum330x is approved by the organizations listed in tabl e 5 . see table 10 and the insulation lifetime section for details regarding recommended maximum work ing voltages for specific cross - isolation waveforms and insulation levels. table 5. ul csa vde recognized under ul 1577 c omponent r ecogn i tion p rogram 1 approved under csa component acce p tance notice #5a certified according to din v vde v 0884- 10 (vde v 0884 -10): 2006-12 2 single protection , 2500 v rms isolation vol t age basic insulation per csa 60950-1- 03 and iec 60950 -1, 800 v rms (1131 v peak) maximum working voltage reinforced insulation per csa 60950-1- 03 and iec 60950 -1, 400 v rms (566 v peak) maximum working voltage reinforced insulation, 560 v peak file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul1577, each adum330x is proof tested by appl ying an insulation test voltage 3000 v rms for 1 second (current leakage detection limit = 5 a). 2 in accordance with din v vde v 0884 - 10 , each adum330x is proof tested by applying an insulation test voltage 1050 v p eak for 1 second (partial discharge detection limit = 5 pc). an asterisk (*) marking branded on the component designates din v vde v 0884 - 10 approval. insulation and safet y- related specifications table 6. parameter symbol value unit conditions rated die lectric insulation voltage 2500 v rms 1- minute duration minimum external air gap (clearance) l(i01) 7.7 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measu red from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index ) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) rev. c | page 10 of 20
data sheet adum3300/adum3301 din v vde v 0884 - 10 (vde v 0884-10) insulation characteristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the asterisk ( *) marking on the package denotes din v vde v 0884 - 10 approval for 560 v peak working voltage. table 7. description conditions symbol characteristic unit install ation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0 110, table 1 2 maximum working insulation voltage v iorm 560 v peak input -to - output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input -to - output test voltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after environmental tests subgroup 1 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 4000 v peak safety - limiting values maximum value allowed in the event of a failure ( see figure 3 ) case temperature t s 150 c side 1 current i s1 265 ma side 2 c urrent i s2 335 ma insulation resistance at t s v io = 500 v r s >10 9 ? case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 05984-003 figure 3 . thermal derating curve, dependence of safety - limiting values with case temperature per din v vde v 0884 - 10 recommended operatin g conditions table 8. parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages 1 v dd1 , v dd2 2.7 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground. see the dc correctnes s and magnetic field immunity section for information on immunity to external mag netic fields. rev. c | page 11 of 20
adum3300/adum3301 data sheet absolute maximum rat ings ambient temperature = 25c, unless otherwise noted. table 9. parameter symbol min max unit storage temperature t st ?65 +150 c ambient operating temperature t a ?40 +105 c supply voltages 1 v dd1 , v dd2 ?0.5 +7.0 v input voltage 1 , 2 v ia , v ib , v ic , v id , v e1 , v e2 ?0.5 v ddi + 0.5 v output voltage 1 , 2 v oa , v ob , v oc , v od ?0.5 v ddo + 0.5 v average o utput current per pin 3 side 1 i o1 ?23 +23 ma side 2 i o2 ?30 +30 ma common - mode transients 4 cm h , cm l ?100 +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi an d v ddo refer to the supply voltages on the input and output sides o f a given channel, respectively. 3 see figure 3 for maximum rated current values for various temperatures . 4 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum rating can cause latch - up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in dicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 10 . maximum continuous working v oltage 1 parameter max unit constraint ac voltage, bipolar waveform 565 v peak 50- year minimum lifetime ac voltage, unipolar waveform basic insulation 1131 v peak maximum approved working voltage per iec 60950 -1 reinforced insulation 560 v peak maxim um approved working voltage per iec 60950 - 1 and vde v 0884 -10 dc voltage basic insulation 1131 v peak maximum approved working voltage per iec 60950 - 1 reinforced insulation 560 v peak maximum approved working voltage per iec 60950 - 1 and vde v 0884 -10 1 refers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more det ails. table 11 . truth table (positive logic) v ix input 1 v ex input 2 v ddi state 1 v ddo state 1 v ox output 1 notes h h or nc powered powered h l h or nc powered powered l x l powered powered z x h or nc unpowered powered h outputs return to the input state wit hin 1 s of v ddi power restor a tion x l unpowered powered z x x powered unpowered indeterminate outputs return to the input state within 1 s of v ddo power restor a tion if v ex state is h or nc outputs return to high impedance state within 8 ns of v ddo pow er restoration if v ex state is l 1 v ix and v ox refer to the input and output signals of a given channel (a, b, or c). v ex refers to the output enable signal on the same side as the v ox outpu ts. v ddi and v ddo refer to the supply voltages on the input and output sides of the given channel, respectively. 2 in noisy environments, connecting v ex to an external logic high or low is recommended. rev. c | page 12 of 20
data sheet adum3300/adum3301 rev. c | page 13 of 20 pin configurations and function descriptions v dd1 1 gnd 1 * 2 v ia 3 v ib 4 v dd2 16 gnd 2 ** 15 v oa 14 v ob 13 v ic 5 v oc 12 nc 6 nc 11 nc 7 v e2 10 gnd 1 * 8 gnd 2 ** 9 nc = no connect adum3300 top view (not to scale) 05984-004 *pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. **pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. in noisy environments, connecting output enables (pin 7 for adum3301 and pin 10 for all models) to an external logic high or low is recommended. figure 4. adum3300 pin configuration table 12. adum3300 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6, 7, 11 nc no connect. 9, 15 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa , v ob , and v oc outputs are enabled when v e2 is high or disconnected. v oa , v ob , and v oc outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
adum3300/adum3301 data sheet rev. c | page 14 of 20 v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 ** 15 v oa 14 v ob 13 v oc 5 v ic 12 nc 6 nc 11 v e1 7 v e2 10 *gnd 1 8 gnd 2 ** 9 nc = no connect adum3301 top view (not to scale) 05984-005 *pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. * *pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. figure 5. adum3301 pin configuration table 13. adum3301 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6, 11 nc no connect. 7 v e1 output enable 1. active high logic input. v oc output is enabled when v e1 is high or disconnected. v oc is disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 9, 15 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa and v ob outputs are enabled when v e2 is high or disconnected. v oa and v ob outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 1, 2.7 v to 5.5 v.
data sheet adum3300/adum3301 typical performance characteristics data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 05984-006 15 10 5 figure 6 . typical input supply current per channel vs. data rate (no load) data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 05984-007 15 10 5 figure 7 . typical output supply current per channel vs. data rate (no load) data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 05984-008 15 10 5 figure 8 . typical output supply curre nt per channel vs. data rate (15 pf output load) data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05984-009 60 40 20 figure 9 . typical adum3300 v dd1 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05984-010 60 40 20 figure 10 . typical adum3300 v dd2 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05984-011 60 40 20 figure 11 . typical adum3301 v dd1 supply current vs. data rate for 5 v and 3 v operation rev. c | page 15 of 20
adum3300/adum3301 data sheet data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05984-012 60 40 20 figure 12 . typical adum3301 v dd2 supply current vs. data rate for 5 v and 3 v operation temperature (c) propagation delay (ns) ?50 ?25 25 30 35 40 0 50 75 25 100 3v 5v 05984-019 figure 13 . propagation delay vs. temperature, c grade rev. c | page 16 of 20
data sheet adum3300/adum3301 application informat ion pc board layout the adum330x digital isola tor requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 14 ). bypass capacitors are most conve n iently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v dd2 . the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm . bypas s ing between pi n 1 and pin 8 and between pin 9 and pin 16 should be considered unless the ground pair on each package side is connected close to the package. v dd1 gnd 1 v ia v ib v ic/oc nc v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc/ic nc v e2 gnd 2 05984-015 f igure 14 . recommended printed circuit board layout in applications involving high com mon - mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally a f fects all pins on a given component side. f ailure to ensure this could cause voltage differentials between pins exceeding the devices absolute maximum ra tings , thereby leading to latch - up or permanent damage. see the an - 1109 application note for board layout guidelines. system - level esd considerat ions and enhancements system - level esd reliability (for example, per iec 61000 -4- x) is highly dependent on system design , which varies widely by application. the adum330x incorporate many enhancements to make esd reliability less dependent on system design. the enhancements include ? esd protection cells added to all input/output interfaces. ? key metal trace resistances reduced using wider geomet r y a nd paralleling of lines with vias. ? the scr effect inherent in cmos devices minimized by use of guarding and isolation technique between pmos and nmos devices. ? areas of high electric field concentration eliminated using 45 corners on metal traces. ? supp ly pin overvoltage prevented with larger esd clamps between each supply pin and its respective ground. while the adum330x improve system - level esd reliability, they are no substitute for a robust system - level design. see application note an - 793 esd/latch - up considerations with i coupler isolation products for detailed recommendations on board layout and system - level design. propagation delay - related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propag a tion delay to a logic low output can differ from the propagation delay to a logic high. input (v ix ) output (v ox ) t plh t phl 50% 50% 05984-016 f ig ure 15 . propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how acc u rately the input signals timing is preserved. channel - to - channel mat ching refers to the maximum amount the propagation delay differs between channels within a si n gle adum330x component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum330x comp o nents operating under the same conditions. dc correctness and m agnetic field imm u nity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the tran s former. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more tha n ~1 s, a per i odic set of refresh pulses indicativ e of the correct input state is sent to ensure dc correctness at the output. if the decoder r e ceives no internal pulses of more than about 5 s, the input side is as sumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 11 ) by the watchdog timer circuit. the limitation on the adum330x s magnetic field imm unity is set by the condition in which induced voltage in the transformers receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3 v operating conditi on of the adum330x is examined because it represents the most susceptible mode of operation. rev. c | page 17 of 20
adum3300/adum3301 data sheet the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = (?d /dt ) r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). r n is the radius of the n th t urn in the receiving coil (cm). n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum330x and an imposed requirement that the induced voltage is at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 16. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 05984-017 figure 16 . maximum allowable external ma gnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a vol t age of 0.25 v at the receiving coil. this is about 50% of the sen s ing threshold and does not cause a faulty output tra nsition. sim i larly, if such an event were to occur during a transmitted pulse (and was of the worst - case polarity), it would reduce the r e ceived pulse from >1.0 v to 0.75 v still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to sp e cific current magnitudes at given distances from the adum330x transformers. figure 17 expresses these allowable current ma gnitudes as a function of frequency for selected di s tances. the adum330x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component (see figure 17 ). for the 1 mhz example noted, a 0.5 ka current would have to be placed 5 mm away from the adum330x to affect the components opera tion. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 05984-018 figure 17 . maximum allowable current for various current - to - adum330x spacing s note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum330x isol a tor is a function of the supply voltage, the channels data rate, and the channels output load. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi ( q ) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half of the input data rate expressed in units of mbps. f r is the input stage refresh rate (mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent su p ply currents (ma). to calculate the total i dd1 and i dd2 supply current, the supply currents for each input and output channel corresponding to v dd 1 and v dd2 are calculated and totaled. figure 6 provides per - channel input supply curr ent as a function of data rate. figure 7 and figure 8 provide per - channel output supply c urrent as a function of data rate for an unloaded output condition and for a 15 pf output condition, respectively. figure 9 through figure 12 pr o vide tot al v dd1 and v dd2 supply current as a function of da ta rate for adum3300 / adum3301 channel configurations. rev. c | page 18 of 20
data sheet adum3300/adum3301 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period . the rate of insulation degradation is depend e nt on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regul atory age ncies, analog devices executes an extensive set of evaluations to determine the lif e time of the insulation structure within the adum330x . a nalog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. t hese factors allow calculation of the time to failure at the actual working voltage . the values shown in table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum csa/vde approved working vol t age s. in many cases, the approved working voltage is higher than 50 - year service life vo ltage. operation at these high working voltages can lead to shortened insulation life. t he insulation lifetime of the adum330x depends on the voltage waveform type imposed across the isol a tion barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 18 , figure 19 , and figure 20 illustrate the se different isolation voltage wav e forms. bipolar ac voltage is the most stringent environment. the goal of a 50 - year operating lifetime under the ac bipolar condition determines the analog devices recommended maximum working volta ge. in the case of unipolar ac or dc voltage, the stress on the insula - tion is significantly lower. this allows operation at higher working voltages while still achieving a 50- year service life. the working voltages listed in table 10 can be applied while maintaining the 50- year minimum lifetime , provided that t he voltage conforms to either the unipolar ac or dc voltage cases. any cross - insulation voltage waveform that does not conform to figure 19 or figure 20 should be treated as a bipolar ac waveform , and its peak volt age should be limited to the 50 - year lifetime voltage value listed in table 10. note that the vol tage presented in figure 19 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 05984-020 figure 18 . bipolar ac waveform 0v rated peak voltage 05984-021 figure 19 . unipolar ac waveform 0v rated peak voltage 05984-022 figure 20 . dc waveform rev. c | page 19 of 20
adum3300/adum3301 data sheet outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 21 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimension s shown in millimeters and (inches) ordering guide model 1 , 2 temperature range ( c) number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse w idth distortion (ns) package option 3 adum3300arwz ?40 to +105 3 0 1 100 40 rw -16 adum3300brwz ?40 to +105 3 0 10 50 3 rw -16 adum3300crwz ?40 to +105 3 0 90 32 2 rw -16 adum3301arwz ?40 to +105 2 1 1 100 40 rw-16 adum3301brwz ?40 to +105 2 1 10 50 3 rw -16 adum3301crwz ?40 to +105 2 1 90 32 2 rw -16 1 z = rohs compliant part. 2 tape and reel are availab le. the addition of an - rl suffix designates a 13 (1,000 units) tape and reel option. 3 rw - 16 = 16 - lead wide body soic. ? 2006 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05984 -0- 4/14(c) rev. c | page 20 of 20

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